0,Enabled, fail safe clock monitor is enabled
0,Enabled, fail safe clock monitor is disabled
0,Disabled, fail safe clock monitor is disabled
0,Primary Oscillator
0,Internal Low-Power RC Oscillator
0,Internal Fast RC Oscillator
0,Low-Power 32 KHz Oscillator
0,0000
0,0101
0,0100
0,0011
0,0110
0,0111
0,1001
0,1010
0,1011
0,1100
0,0001
0,0010
0,1000
0,1101
0,1110
0,1111
0,00000
0,00001
0,00010
0,00011
0,00100
0,00101
0,00110
0,00111
0,01000
0,01001
0,01010
0,01011
0,01100
0,01101
0,01110
0,01111
0,10001
0,10010
0,10011
0,10100
0,10101
0,10110
0,10111
0,XTL oscillator
0,FRC w/PLL 4x
0,FRC w/PLL 16x
0,XT w/PLL 8x
0,XT w/PLL 4x
0,XT w/PLL 16x
0,ERCIO
0,ERC
0,FRC w/PLL 8x
0,ECIO w/PLL 4x 
0,ECIO w/PLL 8x 
0,ECIO w/PLL 16x 
0,ECIO
0,Alternate Oscillator
0,HS/3 w/PLL 16x
0,HS/3 w/PLL 8x
0,HS/3 w/PLL 4x
0,HS/2 w/PLL 16x
0,HS/2 w/PLL 8x
0,HS/2 w/PLL 4x
0,1:3
0,1:5
0,1:6
0,1:7
0,1:9
0,1:10
0,1:11
0,1:12
0,1:13
0,1:14
0,1:15
0,Watchdog enableed
0,Watchdog disabled
0,MCLR pin disabled
0,PORT register
0,PWM module
0,4 ms
0,16 ms
0,64 ms
0,Not protected
0,EMUC and EMUD
0,EMUC1 and EMUD1
0,EMUC2 and EMUD2
0,EMUC3 and EMUD3
0,Operational mode
0,Debug/Emulation mode
0,Chip-on Emulation mode
255,Enables writing
255,Enables erasing
255,Disables erasing
255,Disables writing
0,Boot program memory write-protected
255,No Boot Segment
0,Standard security, Small-size Boot Program Flash
0,Standard security, Medium-sized Boot Program Flash
0,Standard security, Large-sized Boot Program Flash
255,High security, Small-sized Boot Program Flash
255,High security, Medium-sized Boot Program Flash
255,High security, Large-sized Boot Program Flash
255,No RAM is reserved for Boot Segment
255,Small-sized Boot RAM
255,Medium-sized Boot RAM
255,Large-sized Boot RAM
255,No Data RAM is reserved for Secure Segment
255,Small-sized Secure RAM
255,Medium-sized Secure RAM 
255,Large-sized Secure RAM
255,Code protection is disabled
255,Standard security code protection is enabled
255,High security code protection is enaled
255,General Segment program memory is write-protected
255,Start up device with user-selected oscillator source
255,Temperature protection enabled
255,LPRC oscillator
255,Secondary oscillator
255,Primary oscillator with PLL
255,Internal Fast RC oscillator with PLL
255,Allow multiple reconfigurations
255,OSC2 is general purpose digital I/0 pin
255,primary oscillator disabled
255,HS crystal oscillator mode
255,XT crystal oscillator mode
255,EC mode
255,Watchdog enabled/disabled by user software 
255,Watchdog timer in Window mode
255,PWM module low-side output pins have active-low output polarity
255,I2C mapped to ASDA1/SACL1 pins
255,PWRT=128ms
255,PWRT=64ms
255,PWRT=32ms
255,PWRT=16ms
255,PWRT=8ms
255,PWRT=4ms
255,PWRT=2ms
0,PWRT Disabled
255,Device will reset in Clip-On Emulator mode
255,JTAG disabled
255,Communicate on PGC1/EMUC1 and PGD1/EMUD1
255,Communicate on PGC2/EMUC2 and PGD2/EMUD2
255,Communicate on PGC3/EMUC3 and PGD3/EMUD3
255,No Secure Segment
255,Standard security, Small-sized Secure Proqram Flash
255,Standard security, Large-sized Secure Program Flash
255,Standard security, Medium-sized Secure Program Flash
255,High Security, Small-sized Secure Program Flash
255,High security, Medium-sized Secure Program Flash
255,High security, Large-sized Secure Program Flash
255,Secure program memory is write-protected
255,General Segment program memory is not write-protected
255,Start up device with FRC, then automatically switch to the user-selected oscillator source when ready
255,Temperature protection disabled
255,Allow only one reconfiguration
255,OSC2 is clock output
255,Watchdog allways enabled
255,Watchdog timer in Non-Window mode
255,PWM module pins controlled by PORT register at device Reset
255,PWM module pins controlled by PWM module at device RESET
255,PWM module low-side output pins have active-high output polarity
255,PWM module high-side output pins have active-high output polarity
255,PWM module high-side output pins have active-low output polarity
255,I2C mapped to SDA1/SCL1 pins
255,Device will reset in User mode
255,Device will reset in Debug mode
255,Device will reset in Operational mode
255,JTAG enabled
255,Boot Segment program memory is not write-protected
255,Secure Segment program memory is not write-protected
255,Clock switching is disabled, Fail-Safe Clock Monitor is disabled
255,Clock switching is enabled, Fail-Safe Clock Monitor is disabled
255,Clock switching is enabled, Fail-Safe Clock Monitor is enabled
255,No Data EEPROM is reserved for Boot segment
255,Data EEPROM is reserved for Boot segment
255,High security, Large-sized Boot Program Flash  
0,Large-sized Secure Data EEPROM
0,Medium-sized Secure Data EEPROM
255,Small-sized Secure Data EEPROM
255,No Data EEPROM is reserved for Secure Segment
255,Device will reset in Clip-on Emulation mode
255,Watchdog Timer always enabled
255,Watchdog Timer enabled/disabled by user software
255,User program memory is not write-protected
255,User program memory is write-protected
255,User program memory is code-protected
255,User program memory is not code-protected
0,Watchdog Timer in Window mode; FWDTEN musr be '1'
255,Default location for SCL1/SDA1 pins
255,Alternate location for SCL1/SDA1 pins
255,Fast RC (FRC) oscillator
255,Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
255,Primary (XT, HS, EC) oscillator
255,Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
255,Secondary (SOSC) oscillator
255,Low-Power RC (LPRC) oscillator
255,Reserved, defaults to FRC oscillator
255,Internal Fast RC (FRCDIV) oscillator with postscaler
255,Two-Speed Start-up enabled
255,Two-Speed Start-up disabled
255,EC (External Clock) mode
0,Boot Segment ends at 0x0003FF
0,Boot Segment ends at 0x0007FF
0,Boot Segment ends at 0x000FFF
255,High Range: nominal FRC frequency is 14.1 MHz
255,Low Range: nominal FRC frequency is 9.7 MHz
255,Communicate on PGC/EMUC and PGD/EMUD
255,WDTE
255,Flex
255,Prog
255,SPI
255,direct_out
255,tri_out
255,loop_out
255,loop_delay_out
255,flex_gen
255,spi_gen
255,prog_gen
0,BOR is enabled
255,BOR is disabled
255,Last page and Flash Configuration words are not protected
255,Last page and Flash Configuration Words are code-protected
255,Segment code Protection disabled
255,Segment code protection enabled
0,Protected Code segment lower boundary
255,Protected Code segment upper boundary
255,Regulator is disabled
255,Regulator is enabled
255,Emulator function are shared with PGEC1/PGED1
255,Emulator functions are shared with PGEC2/PGED2
255,Emulator functions are shared with PGEC3/PGED3
255,Oscillator input divided by 12
255,Oscillator input divided by 10
255,Oscillator input divided by 6
255,Oscillator input divided by 5
255,Oscillator input divided by 4
255,Oscillator input divided by 3
255,Oscillator input divided by 2
255,Oscillator input used directly
0,Application Section
0,Boot Section
0,Application and Boot Sections
255,EPROM mode
255,Write protect
255,not protected
255,Copy protect
255,Clock switch to PLL source waits for valid PLL lock signal
255,Clock switch to PLL source ignores PLL lock signal
255,Clock switch to PLL source will wait until the PLL lock signal is valid
255,Clock switch will not wait for the PLL lock signal
255,Internal Fast RC (FRC) oscillator with postscaler
255,Internal Fast RC (FRC) oscillator with with divide-by-16
255,Internal Fast RC (FRC) oscillator with PLL
255,Secondary (LP) oscillator
255,FRC oscillator
255,not used
255,Write Protect 85h